1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a circuit arrangement suitable for testing cells arranged in rows and columns in a matrix test block which is formed, together with a non-test block, on an IC chip.
2. Description of the Prior Art
There is known a semiconductor integrated circuit devices having a plurality of logic cells which are coupled via interconnection lines to thereby provide desired logic circuits. Such a semiconductor integrated circuit device is called a logic LSI device. Examples of the logic LSI device are a gate array device, a standard cell array device and a master-slice type integrated circuit device.
The recent advance of fabricating logic LSIs provides a drastically increased number of logic cells arranged in one chip. Currently, logic LSIs having tens to hundreds of thousands of logic cells are available. As an increased number of logic cells is used, an increased number of test patterns must be provided for testing logic LSIs. It takes a long time to produce such test patterns and it is very difficult to determine whether or not desired logic structures are realized correctly. From these points of view, there is a strong need to develop semiconductor integrated circuit devices having built-in test circuits capable of easily verifying logic structures formed therein.
Japanese Laid-Open Patent Application NO. 61-42934 proposes a semiconductor integrated circuit device having a built-in test circuit. FIGS. 1A-1B are a block diagram of the proposed semiconductor integrated circuit device. Referring to this figure, input/output (I/O) areas 2a, 2b, 2c and 2d are provided in peripheral surface portions of a semiconductor chip 1. A plurality of cells (gates) are arranged in a matrix of rows and columns in an inner area surrounded by the I/O areas 2a, 2b, 2c and 2d. These cells are interconnected in accordance with a logic design so that desired logic circuits can be formed.
In order to test the cells, the following arrangements are provided. A plurality of probe lines 3 run at predetermined intervals in a direction in which columns of cells are formed. A plurality of sense lines 4 run at predetermined intervals in a direction in which rows of cells run. A switching transistor 5 is provided at each cross point of the probe lines 3 and the sense lines 4. A logic cell, such as a NAND gate, an AND gate, an OR gate or a NOT gate, is coupled to the corresponding sense line 4 via the transistor 5, the gate terminal of which is connected to the corresponding probe line 3.
A probe line driver 6 for successively selecting one of the probe lines 3 is formed along the I/O area 2c on the left side of the chip 1. A sense amplifier 7 for successively selecting one of the sense lines 4 is formed along the I/O area 2d on the lower side of the chip 1. Further, a test control circuit 8 for controlling the probe line driver 6 and the sense amplifier 7 is provided at a corner of the inner area close to the probe line driver 6 and the sense circuit 7. The test control circuit 8 provides the probe line driver 6 with necessary data for selection as well as a clock signal, in synchronism with which the probe lines 3 are successively selected one by one from the top thereof. When one of the probe lines 3 is turned ON, all transistors 5 coupled to the selected probe line 3 is turned ON, so that the outputs (data) of all cells coupled to the selected transistors 5 are read out to the sense lines 4.
Meanwhile, the sense circuit 7 receives a clock signal from the test control circuit 8 and selects all the sense lines 4 one by one during the time one of the probe lines 3 is being selected. The readout data (information about the potential of the output of the cell) are successively output to an external device via a corresponding I/O pad formed in the I/O area 2a. Alternatively, it is possible to select all the probe lines 3 one by one while one of the select lines 4 is being selected.
With the above-mentioned test, which is called a matrix test, it becomes possible to directly test each cell. It will be noted that conventional test procedures other than the matrix test cannot test each cell but can test the internal circuits in the flip-flop unit. The matrix probing test is also disclosed in U.S. Pat. No. 4,739,250 or U.S. Pat. No. 5,149,993, the disclosure of which is hereby incorporated.
The above-mentioned matrix test is suitable for circuit blocks in which the probe lines 3 and the sense lines 4 are allowed to be arranged in rows and columns. On the other hand, the matrix test is not suitable for circuit blocks of macrocells, such as random access memories, read only memories or central processing units, because they have very complex layout patterns. That is, it is very impossible to arrange the probe lines 3 and the sense lines 4 in rows and columns in the already designed layout patterns. It may be possible to redesign RAMs, ROMs or CPUs having the probe lines 3 and the sense lines 4 without using the already designed layout patterns (resources). However, this is not an efficient procedure since the available resources of layout patterns are not utilized.
Meanwhile, it is possible to fabricate "hybrid" semiconductor integrated circuit chips having matrix test blocks and non-test blocks. The matrix test blocks are blocks which are tested by the matrix test, and the non-test blocks are blocks which are not suitable for the matrix test, such as RAMs, ROMs and CPUs. If the probe lines 3 and the sense lines 4 are provided for such IC chips on the basis of the configuration shown in FIGS. 1A-1B, these lines will be arranged as shown in FIG. 2, in which those parts which are the same as those shown in FIGS. 1A-1B are given the same reference numerals. A matrix test block 10 and a non-test block 9 are arranged, as shown in FIG. 2. The probe line driver 6 runs along the I/O area 2c, and the sense circuit runs along the I/O area 2d. It is actually impossible to arrange the probe lines and the sense lines in the already designed non-test block 10. As a result, it is impossible to test all cells in the matrix test block 9. It may be possible to redesign the non-test block 10 suitable for the matrix test. However, this does not utilize the available resources of layout patterns and needs an extremely large amount of time and an extremely high cost.